A level-shifter is adopted in a driver (a source driver) of a display panel so as to increase amplitude of a signal supplied outside the display panel. Patent documents 1 and 2 are well known documents that disclose arrangements of such a level-shifter.
FIG. 22(a) is a circuit diagram illustrating a circuit configuration of the level-shifter disclosed in the Patent document 1. A level-shifter 110 illustrated in FIG. 22(a) includes: an IN terminal via which an input signal IN is supplied; an INB terminal via which an inversion signal INB of the input signal is supplied; an OUT terminal via which an output signal OUT is supplied; an OUTB terminal via which an inversion signal OUTB of the output signal is supplied; a CMOS inverter circuit 101 including a P-channel MOS transistor 103 (a load transistor) and an N-channel MOS transistor 104 (a driver transistor); a CMOS inverter circuit 102 including a P-channel MOS transistor 105 (a load transistor) and an N-channel MOS transistor 106 (a driver transistor); and two P-channel MOS transistors 107 and 108.
A source of the MOS transistor 107 is connected to a high electric potential side power source (Vdd); a drain of the MOS transistor 107 is connected to a source of the MOS transistor 103; and a gate of the MOS transistor 107 is connected to an output of the CMOS inverter circuit 102.
A source of the MOS transistor 108 is connected to the high electric potential side power source (Vdd); a drain of the MOS transistor 108 is connected to a source of the MOS transistor 102; and a gate of the MOS transistor 108 is connected to an output of the CMOS inverter circuit 101.
Sources of the MOS transistors 104 and 106 are connected to the low electric potential side power source (Vss); an input of the CMONS inverter circuit 101 and the IN terminal are interconnected to each other; an output of the CMOS inverter circuit 101 and the OUTB terminal are interconnected to each other; an input of the CMOS inverter circuit 102 and the INB terminal are interconnected to each other; and an output of the CMOS inverter circuit 102 and the OUT terminal are interconnected to each other.
If, for example, (i) the input signal IN is “H” (Vcc) and (ii) the input inversion signal INB is “L” (Vss) in the level-shifter 110, then the P-channel MOS transistor 103 in the CMOS inverter circuit 101 is capable of supplying a smaller current than the P-channel MOS transistor 105 in the second CMOS inverter circuits; and the N-channel MOS transistor 104 of the CMOS inverter circuit 101 is turned ON, while the N-channel transistor 106 of the CMOS inverter circuit 102 is turned OFF. This causes electric potential of the OUTB terminal to become lower than that of the OUT terminal. As a result, the P-channel MOS transistor 107 supplies a less current than the P-channel MOS transistor 108, so that the electric potential of the OUTB further decreases to be ultimately equal to electric potential of the Vss. This causes the P-channel MOS transistor 107 to be turned OFF whereas the P-channel MOS transistor 108 to be turned ON, thereby resulting in that the electric potential of the OUT terminal becomes equal to that of the Vdd.
Thus, when an input signal is “H” (Vcc), the input signal is level-shifted, so that a signal of Vdd is outputted (see FIGS. 22(b) and 22(c)).
However, according to the circuit configuration, Vcc has to be greater or equal to a threshold electric potential (Vss+ threshold voltage of the N-channel MOS) of the N-channel MOS transistor, in order for the input signal H (Vcc) to turn on the N-channel MOS transistor 104 in the CMOS inverter circuit 101. As such, the level-shifter disclosed in the Patent document 1 cannot level-shift a small input signal (a signal having a small amplitude) of not more than the threshold electric potential of the N-channel MOS transistor.
Meanwhile, the Patent document 2 discloses an arrangement that allows a level-shift of such a small input signal of not more than a threshold electric potential of the N-channel MOS transistor. According to a level-shifter disclosed in the Patent document 2, an input signal having a small amplitude is biased by a constant current source so as to carry out a level-shift with respect to the input signal having such a small amplitude.
(Patent document 1) Japanese Unexamined Patent Application Publication No. 151433/1975 (Tokukai-sho 50-151433) (published on Dec. 5, 1975)
(Patent document 2) Japanese Unexamined Patent Application Publication No. 308091/1999 (Tokukai-hei 11-308091) (published on Nov. 5, 1999)